This invention relates to a circuit for generating the programming voltage for an erasable programmable readonly memory (EPROM, EEPROM), comprising a voltage source which is connected, via a charging resistor, to the memory section to be programmed which is bridged by a (stray) capacitance.
Programmable on-volatile memories of the EPROM (erasable programmable read-only memory) and the EEPROM (electrically erasable programmable read-only memory) type have come into greater use recently because they offer the advantage of easy programming and erasing and renewed programming of the memory unit of an electric computer or microprocessor, so that flexibility as regards the input of new programs is substantially increased. Such an EPROM or EEPROM is usually integrated on a semiconductor body, often together with further arithmetic and control units forming part of the computer or microprocessor.
The programming of an EPROM or EEPROM usually requires an operating voltage which is much higher than the operating voltage of the other semiconductor elements on the semiconductor body, that is to say a voltage just below the breakdown voltage of the semicondcutor junctions, operative in the reverse direction (junction breakdown), of the semiconductor zones constituting the EPROM or EEPROM.
It has been found that EPROMs and EEPROMs are susceptible to failure not only because of the high programming voltages, but also because of the high speed at which the programming voltage applied to these memories is reached. An excessive edge steepness of the increasing programming voltage has an adverse affect on the service life (number of reprogramming operations possible) of an (E)EPROM memory cell because of the peak currents then ocurring in the injecto-oxide of the cell.
An obvious solution to this problem would be the bridging of the memory section to be programmed by a comparatively large capacitor of, for example 1000 pF, but the realization of such a capacitor on the semiconductor body requires a substantial surface area which is, of course, undesirable. Another solution would be the connection of a voltage follower, for example a source follower, in the charging circuit between the voltage source and the memory section, the gate of said follower being connected to ground via a much smaller capacitor (for example 10 pF). Due to the voltage loss between the drain and source of this source follower, however, the available programming voltage would be reduced and that would reduce the programming speed (for example, by a factor 100 slower in practice).
The invention has for an object to provide a circuit whereby the rise time of the programming voltage can be maintained within safe limits to thus mitigate all of the above drawbacks.